A fast and accurate SystemC-AMS model for PLL
conference paper
PLLs have become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on the recently published SystemC/SystemC-AMS (BETA version) language is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Device's ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modeling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems. © 2011 Tech Univ of Lodz.
Topics
hardware description languagemixed-signal modelingPhase Locked LoopSystemC/SystemC-AMSAnalog devicesCadence simulationClosed-loop simulationsDesign environmentDesign timeElectrical systemsMatlab modelsMixed-signal modelingReal measurementsSimulation platformSimulation timeSystem evaluationSystemCSystemC-AMSSystemC/SystemC-AMSVoltage control oscillatorsComputer hardware description languagesDesignIntegrated circuitsJitterMATLABPhase locked loopsComputer simulation
TNO Identifier
461410
ISBN
9788393207503
Article nr.
No.: 6015962
Source title
18th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2011, 16 June 2011 through 18 June 2011, Gliwice
Pages
411-416
Files
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